Constant on-time DC/DC converters are widely used in power conversion due to their excellent load transient response, simple internal configuration and smooth operation mode switching.
FIG. 1 shows a conventional constant on-time DC/DC converter 50. As shown in FIG. 1, a timer U1 receives an input voltage VIN and an output voltage VO of the converter 50, wherein the timer U1 is configured to provide a timing signal with a constant time. Meanwhile, resistors R1 and R2 constitute a feedback loop to divide the output voltage VO to provide a feedback signal VFB to the inverting input terminal of a comparator U2. The non-inverting input terminal of the comparator U2 receives a reference signal VR and the output terminal thereof is electrically coupled to a first input terminal of an AND gate U4. The output terminal of the AND gate U4 is electrically coupled to the set terminal S of a RS flip-flop U5. The reset terminal R of the RS flip-flop U5 receives the output signal of the timer U1. The output terminal Q of the RS flip-flop U5 is electrically coupled to the input terminal of a driver U6, the timer U1 and a minimum off-time circuit U3, respectively. The minimum off-time circuit U3 receives the output signal of the RS flip-flop U5 and provides a low-level signal indicative of a minimum off-time TOFF to a second input terminal of the AND gate U4. The two output signals of the driver U6 respectively drive a high-side switch M1 and a low-side switch M2 of the output stage of the converter 50. Then the output voltage VO is obtained via a filter composed of an inductor L and an ideal capacitor Co. The ESR shown in FIG. 1 is the equivalent series resistance of the ideal capacitor CO.
In operation, the output signal of the comparator U2 is high when the feedback signal VFB is lower than the reference signal VR. If the output signal of the minimum off-time circuit U3 is also high at that time, the AND gate U4 will generate a high level signal to trigger the RS flip-flop U5, so that the output signal of the RS flip-flop U5 is high. Due to the high output signal of the RS flip-flop U5, the high-side switch M1 is turned on and the low-side switch M2 is turned off through the driver U6, so that the output voltage VO increases. When the output voltage VO increases to such an extent that the feedback signal VFB is higher than the reference signal VR, the output signal of the comparator U2 turns to low and thereby the set terminal S of the RS flip-flop U5 is set to be zero, and the output signal of the RS flip-flop U5 maintains the previous state. Meanwhile, the timer U1 starts according to the high output signal of the RS flip-flop U5 until a predetermined value is achieved, i.e., a constant on-time is expired. As a result, the output signal of the timer U1 turns to high, and thereby the RS flip-flop U5 is reset. Thus, the output signal of the RS flip-flop U5 turns to low. Due to the low output signal of the RS flip-flop U5, the high-side switch M1 is turned off and the low-side switch M2 is turned on through the driver U6 so that the output voltage VO decreases. It should be noted that the inductor current decreases linearly when the high-side switch M1 is off and the low-side switch M2 is on. The inductor current may decrease to zero and then flow in reverse if the load current is relatively small. To prevent the inductor current from flowing in reverse, a common approach is to turn off the low-side switch M2 or let it work as an equivalent micro-current source when the inductor current decreases to zero. Meanwhile, the low output signal of the RS flip-flop U5 is also supplied to the minimum off-time circuit U3, so that U3 generates a low output signal which is supplied to the second input terminal of the AND gate U4 to thereby disable the output signal of the AND gate U4 during the minimum off-time TOFF. In other words, the output signal of the AND-GATE U4 is low at this interval no matter the output signal of the comparator U2 is high or low. When the feedback signal VFB decreases to a value lower than the reference signal VR, the output signal of the comparator U2 will turn to high, and if the minimum off-time has expired at that time, the output signal of the AND gate U4 will turn to high to set the RS flip-flop U5, so that the converter 50 enters a new cycle.
Those skilled in the art can realize that the function of the minimum off-time circuit U3 herein is as follows. While the converter 50 is in normal operation, after a constant on-time interval, the output signal of the RS flip-flop U5 turns to low and thereby the high-side switch M1 is turned off and the low-side switch M2 is turned on. Thus, the output voltage VO starts to decrease. Due to noise interference, the comparator U2 may enter a new cycle immediately after the constant on-time interval and then generate a high output signal to thereby set the RS flip-flop U5, which causes the high-side switch M1 to be turned on and the low-side switch M2 to be turned off immediately and the output voltage VO starts to increase. To prevent such a situation, the minimum off-time circuit U3 detects the low signal Q and supplies a low output signal to the AND gate U4 to disable the high output signal produced by the comparator U2 to ensure that the high-side switch M1 is turned off and the low-side switch M2 is turned on within the minimum off-time while the converter 50 is in normal operation.
FIG. 2(a) and FIG. 2(b) illustrate the waveforms of the driving signal of the high-side switch M1, the voltage ripple across the equivalent series resistance ESR, the voltage ripple across the ideal capacitance Co and the output voltage ripple of the converter 50 shown in FIG. 1. As shown in FIG. 2(a) and FIG. 2(b), while the converter 50 is in steady operation, as the equivalent series resistance ESR has a relatively small resistance value compared to the load, the inductor current ripple can be considered to completely flow through the resistance ESR and the ideal capacitance Co. As a result, a ripple voltage across the resistance ESR which is in phase with and amplitude proportional to the inductor current ripple is generated. Meanwhile, the ideal capacitance Co has an integral effect on the current ripple and thereby generates a capacitance ripple voltage which is 90 degree delayed to the inductor current ripple. When the resistance value of the resistance ESR is relatively large, the voltage ripple across the resistance ESR plays a dominant role compared to the voltage ripple across the ideal capacitance Co, thereby the ripple of the output voltage VO of the converter 50 is determined mainly by the voltage ripple across the resistance ESR as shown in FIG. 2(a). Thus the output voltage VO is relatively stable. On the contrary, when the resistance value of the resistance ESR is relatively small, the voltage ripple across the ideal capacitance Co plays a dominant role compared to the voltage ripple across the resistance ESR, Thereby the ripple of the output voltage VO of the converter 50 is determined mainly by the voltage ripple across the ideal capacitance Co. As a result, the system may produce sub-harmonic oscillation and lose stability, as shown in FIG. 2(b).
In sum, an equivalent series resistance ESR with large resistance value is needed in the conventional constant on-time DC/DC converter to stabilize the system. Accordingly, in special applications such as notebook computers, the conventional constant on-time DC/DC converter cannot adopt ceramic capacitors with small size and low price as output capacitors. Instead, a polymer organic semiconductor solid capacitors (sp-cap) is required which are relatively expensive.
Accordingly, there is a need to provide a constant on-time DC/DC converter which stabilizes the system even under the low equivalent series resistance situation, i.e., when the ceramic capacitors are used.